The present invention generally relates to an address manager for use in a memory management system which translates central processing unit multiple-bit memory addresses to be translated to translated addresses and which conveys the translated addresses to a memory control unit. The present invention more particularly relates to an address manager which is fully integrated within a single integrated circuit device along with its associated central processing unit and memory control unit and which provides an alert signal to the memory control unit upon translating a central processing unit memory address.
Memory systems are well known in the art. Such systems are used in many applications including personal computers. Memory systems provide program and operating data to associated central processing units to enable the central processing units to execute program instructions.
Memory systems, such as those incorporating dynamic random access memory (DRAM) devices generally include one or more memory banks wherein each memory bank is divided into pages of, for example, 16 KB pages. In this case, for example, a 256 KB memory bank will include sixteen pages.
In order to access such memories, central processing units provide a multiple-bit address including a first portion which can be used as an index into a 16 KB memory page and a second portion which can be used to generate memory page pointers. In order to provide proper and organized memory utilization, the central processing unit memory address second portion pointers are translated by an address manager translation unit in accordance with stored translation parameters to provide a translated address including the central processing unit memory address first portion which is not translated and a translated second portion which includes an address of the proper page to be accessed.
The translated address is then conveyed to a memory control unit which acts upon the translated address to derive a memory row and column address within the addressed page and row and column address strobe signals to be applied to the memory bank which includes the addressed page. In this manner, the available memory space is efficiently utilized and organized.
In the prior art, the address managers have been integrated within an integrated circuit device separate from the central processing unit integrated circuit device and separate from the memory control unit integrated circuit device. This has caused serious timing delays in the critical timing path for memory address generation. For example, because the address manager has been separately integrated from the memory control unit, prior art address manager integrated circuits have required large transistor buffers to couple the address manager to the memory control unit. Such buffers, because they conduct large currents, are slow in responding to address signals which must be conveyed between the address manager and the memory control unit. The address manager of the present invention overcomes the need for large transistor buffers between the address manager and the memory control unit because the address manager is fully integrated within a single integrated circuit device along with the central processing unit and the memory control unit.
In such systems, central processing units perform accesses to operating system and program memory with addresses which require the aforementioned translation and accesses to slower memory and peripheral devices with addresses which do not require translation. The first mentioned accesses must be performed quickly since these accesses are required to permit the central processing unit to support the entire system. The second mentioned accesses to access peripheral devices, as for example disk drives and external printers, or slower memory and which do not require address translation, are performed rather slowly compared to the first mentioned memory accesses. To insure proper signal timing, the address manager of the present invention includes an alert means which provides an alert signal when it receives an address from its central processing unit that requires translation The alert signal provided to the memory control unit informs the memory control unit that it is translating an address and that the memory control unit should adjust its timing accordingly for generating the aforementioned row and column addresses and row and column address strobe signals.